A higher-level chip workflow makes agents 2.6× faster
LLM agents designed FPGA chips 2.6× faster on average when they worked from higher-level hardware abstractions, then refined the result at RTL, than when they wrote RTL directly. The AHRR workflow uses high-level synthesis to turn agent decisions into hardware, followed by RTL refinement to recover lower-level optimizations. The paper tests it across 11 tasks and says the code and evaluation artifacts are available.