PlaceReasoner-Beta cuts routed timing loss by up to 61.2%
PlaceReasoner-Beta gives chip designers a closed-loop way to place macros, judging layouts with legality checks and downstream physical-design feedback instead of relying mainly on estimated wirelength. Its planner proposes placements from floorplan images, macro specs, and connectivity, then verifiers refine them through implementation and post-route results. On PlaceReasoner-Bench’s 16 fixed-floorplan tasks, it reduced post-route total negative slack by 61.2% on square tasks and 53.0% at 2:1 aspect ratio versus the classical baseline field.